The present invention relates to a semiconductor device provided with a field effect transistor such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an element isolation region, and more particularly to a semiconductor device provided with a dynamic threshold transistor with a gate electrode being electrically connected to a well region and with an element isolation region.
As a technique to achieve considerable reduction in power consumption by decrease of operating voltage in CMOS (Complementary Metal Oxide Semiconductor) circuits using MOSFET, there has been proposed a dynamic threshold transistor (hereinbelow referred to as DTMOS) using a bulk substrate in Japanese Patent Laid-Open Publication HEI No. 10-22462, Japanese Patent Laid-Open Publication No. 2000-82815, and Novel Bulk Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation(SITOS) and Gate to Shallow Well Contact(SSS-C) Processes for Ultra Low Power Dual Gate CMOS, H. Kotaki et al., IEDM Tech. Dig., p459, 1996.
A schematic cross sectional view of N-type and P-type DTMOS is shown in FIG. 13. In FIG. 13, there are shown a substrate 111, an N-type deep well region 112, a P-type deep well region 113, a P-type shallow well region 114, an N-type shallow well region 115, an element isolation region 116, an N-type source region 117, an N-type drain region 118, a P-type source region 119, a P-type drain region 120, a gate insulator 121, a gate electrode 122, an N-type DTMOS 123, and a P-type DTMOS 124. In addition, though not shown in FIG. 13, the gate electrode 122 in the N-type DTMOS 123 is electrically connected to the P-type shallow well region 114 through a contact hole. Similarly, the gate electrode 122 in the P-type DTMOS 124 is electrically connected to the N-type shallow well region 115 through a contact hole. The element isolation region 116 of FIG. 13 is shown in detail in FIG. 14. The element isolation region 116 is made up of a LOCOS (Local Oxidation of Silicon) oxide portion 125 and a trench portion 126.
Hereinbelow, the principle of DTMOS operation will be described in the case of the N-type DTMOS 123 with reference to FIG. 13. In the N-type DTMOS 123, when the gate electrode 122 is in a low potential level (OFF state), the shallow well region 114 is also in a low potential level and so the effective threshold thereof is the same as that of typical MOSFET. Therefore, an OFF-state current value (OFF leakage) thereof is also identical to that of typical MOSFET.
When the gate electrode 122 is in a high potential level (ON state), the shallow well region 114 is also in a high potential level, which decreases the effective threshold due to substrate bias effect, thereby generating driving current larger than that of typical MOSFET. This makes it possible to obtain large driving current while low leakage current being maintained with low power supply voltage.
In the DTMOS 123 and 124, as stated above, each gate electrode 122 is electrically short-circuited to the shallow well regions 114 and 115. Consequently, if the potential of the gate electrode 122 changes, the potential of the shallow well regions 114, 115 also changes. This necessitates electrical isolation of the shallow well region 114, 115 of each DTMOS 123, 124 from shallow well regions of adjacent MOSFET. The trench portion 126 of the element isolation region 116 is configured to have a depth so as to isolate the shallow well regions of adjacent MOSFET from each other. The LOCOS oxide portion 125 of the element isolation region 116 is, for example, provided on an interconnection part of the gate electrode 122, for decreasing capacitance between the gate region and the well region.
Increasing miniaturization of elements makes the distance (Wsd in FIG. 13) from the edge of the gate electrode to the element isolation region smaller and smaller. To cope with this situation, there was fabricated a P-type MOS having a stacked-up type of source and drain regions which makes it possible to minimize the source region and drain region (a structure and fabrication method thereof is disclosed in Japanese Patent Laid-Open Publication No. 2000-82815). As a result of measuring the transistor characteristics thereof, abnormal leakage current was found in the P-type MOS. FIG. 15 shows changes of drain current versus gate voltage, in which a solid line indicates smaller Wsd (Wsd=0.40 xcexcm) and a dashed line indicates larger Wsd (Wsd=1.0 xcexcm).
The leakage current was seen only in P-type MOS whose Wsd is small. Even with the same Wsd, leakage current values showed considerable difference per element. It is noted that these elements stated above are different only in Wsd and are equal in such factors as a gate length, a gate width, and a high impurity concentration of channel. In the example of FIG. 15, when gate voltage is 0 V (the transistor is OFF), off current marks four digits increase in the case of Wsd=0.4 xcexcm compared to the case of Wsd=1.0 xcexcm , which causes leakage current in CMOS circuits, and thereby disturbs reduction of power consumption.
Off leakage failure of P-type MOS stated as the problem to be solved by the present invention may be attributed to the following. That is, bird""s beak generated in the process of LOCOS oxidation approaches the end of the gate electrode, as a result of which stress originated from the bird""s beak causes abnormal dissipation of impurities at the end of the gate electrode or the gate oxide film. Abnormal dissipation of impurities partially reduces impurity concentration of channel, thereby causing increase of off leakage.
For solving the above problem, an object of the present invention is to provide a semiconductor device with use of DTMOS which does not cause increased off leakage failure even if the distance from the end of the gate electrode to the element isolation region is shortened by miniaturization of elements, and to provide a fabrication method thereof.
The present invention provides a semiconductor device, comprising:
a semiconductor substrate;
a first conductive-type deep well region formed inside the semiconductor substrate;
a second conductive-type shallow well region formed in the first conductive-type deep well region;
a dynamic threshold transistor formed on the second conductive-type shallow well region, a gate electrode of the dynamic threshold transistor being short-circuited to the second conductive-type shallow well region;
a shallow element isolation region formed on the second conductive-type shallow well region and composed of STI with a depth shallower than a depth of an interface between the first conductive-type deep well region and the second conductive-type shallow well region; and
a deep element isolation region formed on the first conductive-type deep well region by penetrating through the second conductive-type shallow well region and having a depth deeper than the depth of the interface between the first conductive-type deep well region and the second conductive-type shallow well region.
In this description, the first conductive type refers to either a P type or an N type, whereas the second conductive type refers to an N type if the first conductive type is a P type, and to a P type if the first conductive type is an N type.
According to the above invention, the element isolation region is composed of a deep element isolation region and a shallow element isolation region made of STI. Consequently, even if the dynamic threshold transistor is composed of PMOS, off leakage failure of PMOS is not only prevented due to stress caused by bird""s beak, but also embedding of an insulating film in the element isolation region is facilitated. Further, the element isolation region composed of a deep element isolation region and a shallow element isolation region made of STI makes it possible to decrease element and inter-element margins.
In one embodiment of the present invention, the semiconductor device further comprises:
a second conductive-type deep well region formed inside the semiconductor substrate;
a first conductive-type shallow well region formed in the second conductive-type deep well region;
a dynamic threshold transistor formed on the first conductive-type shallow well region, a gate electrode of the dynamic threshold transistor being short-circuited to the first conductive-type shallow well region;
a shallow element isolation region formed on the first conductive-type shallow well region and composed of STI with a depth shallower than a depth of an interface between the second conductive-type deep well region and the first conductive-type shallow well region;
a deep element isolation region formed on the second conductive-type deep well region by penetrating through the first conductive-type shallow well region and having a depth deeper than the depth of the interface between the second conductive-type deep well region and the first conductive-type shallow well region; and
an interface element isolation region provided at an interface between the first conductive-type and second conductive-type deep well regions and between the first conductive-type and second conductive-type shallow well regions.
The semiconductor device of the above embodiment is structured in a complementary form with use of the semiconductor device of the above-stated invention.
Therefore, the dynamic threshold transistors have symmetrical output characteristics, and power consumption is decreased.
In one embodiment of the present invention, at least one of the deep element isolation regions has an approximately constant width. The approximately constant width makes it easy to form the deep element isolation region.
In one embodiment of the present invention, the dynamic threshold transistor has a stacked-up type structure in which a part of a source region and a part of a drain region of the dynamic threshold transistor exist above a plane formed by a gate insulating film of the dynamic threshold transistor.
According to the above embodiment, forming the source region and the drain region in a stacked-up type makes it easy to decrease depth of interface of the source region and the drain region with the shallow well region.
Also, the source region and the drain region formed in the stacked-up type are considerably reduced in area. Therefore, an area of the element is further decreased, and highly integrated circuits including dynamic threshold transistors are provided.
In one embodiment of the present invention, the interface element isolation region is a complex element isolation region comprising a shallow element isolation region made of STI with a depth shallower than the depth of the interface between the shallow well region and the deep well region and deep element isolation regions disposed on both sides of the shallow element isolation region with a depth deeper than the depth of the interface and an approximately constant width.
According to the above embodiment, compared to the case of simply providing a deep element isolation region with a large width, embedment of an oxide film is facilitated, which makes it relatively easy to form a complex element isolation region with a large width. Since the deep element isolation regions are present on both sides of the shallow element isolation region, there is effectively prevented punchthrough between the first conductive-type deep well region and the first conductive-type shallow well region, or between the second conductive-type deep well region and the second conductive-type shallow well region. Therefore, a plurality of dynamic threshold transistors are effectively isolated with a small element isolation margin.
In one embodiment of the present invention, the interface element isolation region is a complex element isolation region comprising a deep element isolation with a depth deeper than the depth of the interface between the shallow well region and the deep well region and an approximately constant width and shallow element isolation regions disposed on both sides of the deep element isolation region and made of STI with a depth shallower than the depth of the interface.
According to the above embodiment, compared to the case of simply providing a deep element isolation region with a large width, embedment of an oxide film in the complex element isolation region is facilitated, and therefore it makes relatively easy to form a complex element isolation region with a large width. According to the complex element isolation region, effective isolation of the first conductive-type and the second conductive-type shallow well regions is implemented with a small element isolation margin, thereby enabling control of change in threshold values of a dynamic threshold transistor.
The present invention also provides a method for fabricating a semiconductor device having:
a semiconductor substrate;
a first conductive-type deep well region formed inside the semiconductor substrate;
a second conductive-type shallow well region formed in the first conductive-type deep well region;
a dynamic threshold transistor formed on the second conductive-type shallow well region, a gate electrode of the dynamic threshold transistor being short-circuited to the second conductive-type shallow well region;
a shallow element isolation region formed on the second conductive-type shallow well region and composed of STI with a depth shallower than a depth of an interface between the first conductive-type deep well region and the second conductive-type shallow well region; and
a deep element isolation region formed on the first conductive-type deep well region by penetrating through the second conductive-type shallow well region and having an approximately constant width and a depth deeper than the depth of the interface between the first conductive-type deep well region and the second conductive-type shallow well region,
the method comprising the steps of:
forming a first film on a semiconductor substrate;
forming a first open window on the first film;
forming a first isolation trench by etching part of the semiconductor substrate with use of the first film as a mask;
forming a second film on the first film and the first isolation trench;
forming a second open window on the second film;
etching part of the first film with use of the second film as a mask;
forming a second isolation trench by partially etching the semiconductor substrate with use of the first film as a mask; and
depositing an insulating film on the first film, the first isolation trench and the second isolation trench for filling the first isolation trench and the second isolation trench.
According to the invention, the first film functions as a mask for forming the first isolation trench and also as a mask for forming the second isolation trench. This makes it possible to decrease the steps for forming the semiconductor device. In addition, in forming the second isolation trench, the first isolation trench is etched together, which prevents generation of unnecessary difference in the first isolation trench.
In one embodiment of the present invention the first film is a laminated film made of a silicon oxide film and a silicon nitride film, the second film is a photoresist, and the insulating film is an oxide film.
According to the above embodiment, a laminated film resistant to ashing or hydrofluorination is used as the first film required to function as a mask twice. Meanwhile a film made of photoresist easily removable by ashing is used as the second film which should function as a mask only once. This may simplify the method for fabricating the semiconductor device.